In the fabrication of multi-level-metal integrated circuits, it is known to provide a first level of metalization which makes direct ohmic contact with a chosen area of a semiconductor substrate, such as silicon, and thereafter deposit a second level of metalization above and physically separated from the first layer of metalization. The second level of metalization will normally be insulated from the first level of metalization by a chosen dielectric material, such as silicon dioxide, which is referred to in the art as the "inter-layer dielectric." In structures where only two levels of metalization are used, the acronym "DLM" has been used to refer to "double-level-metal" structures and integrated circuits.
In order to make desired vertical electrical interconnections between the first and second levels of metalization, one practice has been to use conventional ultraviolet (UV) photolithographic masking and etching techniques to provide a protective photoresist coating of a desired geometry on top of the inter-layer dielectric and then etch openings or vias through this dielectric layer in areas exposed by openings in the photoresist coating. After this etching step was completed, the deposition of the second layer of metalization was made on the inter-layer dielectric and through these openings or vias to make vertical contact to the first layer of metalization.
While the above process has been satisfactory for processing smooth uniform layers of metalization, it has not been entirely satisfactory in maintaining acceptable yields where the layers of metalization had hillocks or spikes thereon. These hillocks or spikes are in the form of sharp up-standing imperfections in the metalization which may sometime extend one to two micrometers above the horizontal surface of the metalization. These spikes are produced by uneven nucleation in the metal which takes place in the metal deposition and cooling process.
The reason for the unacceptable yields was a failure of the above photoresist coating to conform with and vertically replicate the geometry of these hillocks or spikes. Thus, the photoresist coating did not adequately conform to and cover the inter-layer dielectic in areas where this dielectric layer was vertically "pushed up" by the underlying hillocks or spikes on the first layer of metalization. As a general rule, the inter-layer dielectric conforms quite satisfactorily to the geometry of the underlying metal hillocks or spikes, but this is not the case with the photoresist coating which is deposited over the subsequently formed protrusions in the inter-layer dielectric replicating the hillocks or spikes in the metal. This non-conformity, in turn, caused these protrusions in the inter-layer dielectric to extend in some areas completely through the overlying photoresist coating and thereby subsequently produce undesirable electrical shorts between the first and second levels of metalization. This problem of electrical shorting will become more readily apparent in the following description of the present invention.
In order to solve the above problem, it has been proposed to merely increase the thickness of the photoresist coating in an attempt to fully cover protrusions in the inter-layer dielectric at all times. However, this approach has also proven unsatisfactory since the solvent in the added photoresist tends to dissolve the earlier deposited photoresist material, with the end result being unacceptable conformity of the thicker photoresist layer and unacceptable electrical shorts still being produced between the first and second levels of metalization.